实验模块原理图

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1、AEDK5196ET实验模块原理AEDK5196ET实验系统主板采用模块化设计，由二十多个硬件模块组成。用户可用它组合成各种各样的硬件实验。1MODEL162256存储器ALED474LS373ADI4AD27AD38AD413ADS14AD617AD71SADQ3C11DDDDDDDD0123456701234567QQQQQQQQEEOLD1974LS373AD94AD107AD118AD1213AD1314AD1417AD1518AD3301234567DDDDDDDD11EEOL2A062256

2、01234567QQQQOQQQ2A8987654325242123226110ft0—ft1401234012345678911111AAAAAAAAAAAAAAARAMRD/22RhMI,IR/2TRAM/20"0123456?DDDDDDDD111212TsTeT718F9M0DEL162256存储器实验机上RAM,可作程序区或数据区，地址为0-7FFFH。2MODEL2……8279键盘显示BID28：E740710^illRN6220*8RESPACK8piTTLOvjOr-ooI*I00oLx

3、JLi.CLKRESET01234567QRSDR0012301234567L

4、L」L」LLLLLL」ssssRRRRRRRR233234353839SHIFTCNTLZS3637cmm，LOpD+g<■<0y1欠2y3y4，6y7xM0DEL28279键盘显示8279数据口地址是0FF80H和状态口地址是0FF82HR254.7k232。TXD788251/1lrRD/13^UR/10^A112CCLK5126RESET21AD0-75D0TxDDID2TxRDVD3TxCLKC

5、LKCTSRESETRTSD368251272821915918314：＞2516OO22241723RSCLKD31：A4LS125D31：D74LS125才Gi12CPU-TXD2k771■R44Q65D31：B74LS1259C60.lu232.RXDk672.R4:8ICPU.RXDD31：C74LS1251C4[~~0.1u7T34C5_J2~0.iu7T~s232.TX[:■11232,RXD12933A+i+112ccc2TL12CT1TT+IHvNVsooR12TT1112RRON9oo

6、12RRin丄C7~p.1u1413M0DEL38251可编程串行通讯实验8251数据口地址0FFA0H,状态门地址0FFA2H。4MODEL4-—138译码电路A8D274LS133A92A103A156A14A13<•-ABC0123VVVV15800012EE56r-VVV•1481008208128308118408108500986098700.麵..一.r-.M0DEL4138译码电路空间地址8000-87FFH，由D274LS138分成8个片选信号，其屮：Y0:8()()()HY1:810

7、0HY2:8200HY3:8300HY4:8400HY5:8500HY6:8600HY7:8700H012345672345111111113333PPPPPPPPPPPPM0DEL56MODEL6开关量输入单片机I/O线K1K2K3K4K5K6K7K8M0DEL6开关量输入开关向上拨至H端，输出孔为”1";开关向下拨至L端，输出孔为”0”7MODEL7可编程并行口8255D0-D9D343255S/RD/5A1A2D0PA0D1PA1D2PA2D3PA3D4PA4D5PA5D6PA6D7PA?RDPB

8、0URPB1A0PB2A1PB3RESETPB4CSPB5PB6PB?PCSPCIPC2PC3PC4PC5PC6PC?3134333230292827UR/3698RST3563PA1:2PA2:1PA3:40PA4:39PA5:38PAS:37PA7:18PB0.19PE:1:20PB2:21PE:3:22PB4:23PE:5:24PE!6:25PB7:14PC0.15PCI*16PC2：17PC3:13PC4:12PC5:11PC6:1