ddr3设计调试

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1、DDR3设计配置：1.关于配置寄存器：部分配置寄存器基地址在0x2100_0000#defineDDR3.BASE_ADDR(0x21000000)#dcfincDDR一SDCFG(*(unsigncdint*)(DDR3—BASE_ADDR+0x00000008))#dcfincDDR.SDRFC(^(unsignedint*)(DDR3_BASE_ADDR+0x00000010))井defineDDR.SDTIMI(*(unsignedint*)(DDR3_BASE.ADDR+0x(X)000018))#defi

2、neDDR_SDTIM2(*(unsignedint*)(DDR3_BASE_ADDR+0x0000002()))#defineDDR—SDTIM3(*(unsignedint*)(DDR3_BASE_ADDR+0x00000028))#dcfincDDR.PMCTL(*(unsigncdint*)(DDR3_BASR_ADDR+0x00000038))#defincRDWRJLVL—RMP一WIN(^(unsignedinl*)(DDR3_BASE_ADDR+0x00000004))井defineRDWR_LVL_

3、RMP_CTRL(*(unsignedint*)(DDR3_BASE.ADDR+0x()000()008))#deflneRDWR_LVL_CTRL(*(unsignedint*)(DDR3_BASE_ADDR+()x(M)(M)(M)DC))#defineDDR—ZQCFG「(unsignedint*)(DDR3一BASE—ADDR+0x000000C8))#dcfincDDR_PHYCTRL(*(unsigncdint*)(DDR3_BASR_ADDR+OxOO<)O<)OR4))大部分寄存器位于chip-lev

4、elregisters0x0262_0000#defineDDR3PLLCTL0(*(unsignedint*)(OxO262O33O))#dcfincDDR3PLLCTL1(^(unsignedint*)(0x02620334))#defincDATA0_WRLVLJNIT_RATIO(^(unsignedinl*)(0x0262040C))#defineDATA1_WRLVLJNIT^RATIO(^(unsignedint*)(0x02620410))#defineDATA2_WRLVL_IN1T_RATIO(^

5、(unsignedint*)(0x()262()414))#defineDATA3_VRLVLJNIT_RATIO(*(unsignedint*)(OxO262O4!8))#dcfincDATA4_WRLVLJN!T_RATIO(*(unsigncdint*)(0x026204IC)>#defincDATA5_WRLVLJNIT_RATIO(^(unsignedinl*)(0x02620420))#defineDATA6_WRLVLJNIT^RATIO(^(unsignedint*)(0x02620424))#de

6、fineDATA7_WRLVL_IN1T_RATIO(^(unsignedint*)(0x()262()428))#defineDATA8_VRLVLJNIT_RATIO(*(unsignedint*)(OxO262O42C))#dcfincDATAO_GTLVLJNIT_RATIO(*(unsigncdint*)(0x0262()43C))#defincDATA1_GTLVUINIT_RATIO(^(unsignedint*)(0x02620440))#defineDATA2—GTLVLJN1T_RATIO(^(

7、unsignedint*)(0x02620444))#defineDATA3_GTLVL_INIT_RATIO(^(unsignedint*)(OxO262()448))#defineDATA

8、fineDATA7_GTLVLJN1T_RATIO(^(unsignedint*)(OxO262O458))#defineDATA8_GTLVL_INIT_RATIO(^(unsignedint*)(0x()262045C))#defineDDR3.CONFIG_REG_0(*(unsignedint*)(0x02620404))#dcfinc