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《adda等一些芯片的verilog程序》由会员上传分享，免费在线阅读，更多相关内容在学术论文-天天文库。
1、/*AD0809modulev1.0workupto5Msample=25us40khzfornormalclk=2.5Msample=30us33khz*/modulead0809(clkin,adclk,eoc,st,ale,datain,oe,dataout);inputclkin;inputeoc;input[7:0]datain;outputst;outputale;outputoe;outputadclk;output[7:0]dataout;regadclk;reg[7:0]dataout;regst;regoe;regale;//frequencedivid
2、erforADparameterDiv_adclk=8'd9;//(9+1)*2=20adclk=2.5MparameterDiv_clk_state=4'd4;//(4+1)*2=10clk_state=5Mreg[8:0]div_cnt_ad;//frequencedivcntreg[3:0]div_cnt_state;regclk_state;always@(negedgeclkin)beginif(div_cnt_ad!=Div_adclk)div_cnt_ad<=div_cnt_ad+1'b1;elsebegindiv_cnt_ad<=0;adclk<=~adcl
3、k;endif(div_cnt_state!=Div_clk_state)div_cnt_state<=div_cnt_state+1'b1;elsebegindiv_cnt_state<=0;clk_state<=~clk_state;endend/*ADconvert*/reg[3:0]state;reg[7:0]delay;initialbeginstate<=4'd0;endalways@(negedgeclk_state)begincase(state)4'd0:begin//clearallst<=1'b0;oe<=1'b0;ale<=1'b0;delay<=8
4、'h00;state<=4'd1;end4'd1:begin//alelatchale<=1'b1;state<=4'd2;end4'd2:begin//strasingst<=1'b1;state<=4'd3;end4'd3:begin//alefallingale<=1'b0;state<=4'd4;end4'd4:begin//stfallingst<=1'b0;state<=4'd5;end4'd5:begin//eocdelayafterst;8clock+2us=26stata_clkdelay<=delay+1'b1;if(delay==8'd26)state
5、<=4'd6;elsestate<=4'd5;end4'd6:begin//testeoc(convetefinished);if(eoc)state<=4'd7;elsestate<=4'd6;end4'd7:begin//outenableoe<=1'b1;state<=4'd8;end4'd8:begin//takedatadataout<=datain;state<=4'd9;end4'd9:begin//outunable;returnoe<=1'b0;state<=4'd0;enddefault:state<=4'd0;endcaseendendmodule/*
6、clk=5MhzT=0.2usthedistance=0.2*1000_000*data*340m/s*/modulechao(clk,start,reset,trig,echo,data,success,time_out);inputclk,start,reset,echo;outputtrig,data,success,time_out;regtrig,time_out,success;reg[31:0]data;reg[3:0]state;parameterPrepare=4'd1;parameterDelay_trig=4'd2;parameterEcho_rais
7、ing=4'd3;parameterEcho_falling=4'd4;parameterTime_out=4'd5;parameterSuccess=4'd6;reg[7:0]dely;//60*0.2=12usreg[31:0]timer;//iftimerisbiggerthan0x1e848(farthan4.0m),timeoutalways@(negedgeclkornegedgereset)beginif(!reset)beginstate<=Prepare;endelsebegincase(stat
