4013 cmos 带置位-复位的双d触发器

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1、CD4013BCDualD-TypeFlip-FlopOctober1987RevisedJanuary1999CD4013BCDualD-TypeFlip-FlopGeneralDescriptionFeaturesTheCD4013BdualD-typeflip-flopisamonolithiccomple-■Widesupplyvoltagerange:3.0Vto15VmentaryMOS(CMOS)integratedcircuitconstructedwith■Highnoiseimmunity:0.45VDD(typ.)N-andP-channelenha

2、ncementmodetransistors.Each■LowpowerTTL:fanoutof2driving74Lflip-flophasindependentdata,set,reset,andclockinputsand“Q”and“Q”outputs.Thesedevicescanbeusedforcompatibility:or1driving74LSshiftregisterapplications,andbyconnecting“Q”outputtothedatainput,forcounterandtoggleapplications.TheApplic

3、ationslogiclevelpresentatthe“D”inputistransferredtotheQ•Automotiveoutputduringthepositive-goingtransitionoftheclockpulse.Settingorresettingisindependentoftheclockand•Dataterminalsisaccomplishedbyahighlevelonthesetorresetline•Instrumentationrespectively.•Medicalelectronics•Alarmsystem•Indu

4、strialelectronics•Remotemetering•ComputersOrderingCode:OrderNumberPackageNumberPackageDescriptionCD4013BCMM14A14-LeadSmallOutlineIntegratedCircuit(SOIC),JEDECMS-120,0.150”NarrowCD4013BCSJM14D14-LeadSmallOutlinePackage(SOP),EIAJTYPEII,5.3mmWideCD4013BCNN14A14-LeadDual-In-LinePackage(PDIP),

5、JEDECMS-001,0.300”WideDevicesalsoavailableinTapeandReel.Specifybyappendingthesuffixletter“X”totheorderingcode.ConnectionDiagramTruthTablePinAssignmentsforDIP,SOICandSOPCLDRSQQ(Note1)0000110010x00QQxx1001xx0110xx1111NoChangex=Don'tCareCaseNote1:LevelChangeTopView©1999FairchildSemiconduc

6、torCorporationDS005946.prfwww.fairchildsemi.comSchematicDiagramsCD4013BCLogicDiagramwww.fairchildsemi.com2CD4013BCAbsoluteMaximumRatings(Note2)RecommendedOperating(Note3)Conditions(Note3)DCSupplyVoltage(VDD)-0.5VDCto+18VDCDCSupplyVoltage(VDD)+3VDCto+15VDCInputVoltage(VIN)-0.5VDCtoVDD+0.5V

7、DCInputVoltage(VIN)0VDCtoVDDVDCStorageTemperatureRange(TS)-65°Cto+150°COperatingTemperatureRange(TA)-40°Cto+85°CPowerDissipation(PD)Note2:“AbsoluteMaximumRatings”arethosevaluesbeyondwhichthesafetyofthedevicecannotbeguaranteed,theyarenotmeanttoimplythatDual-In-Line70