【vhdl 程序举例大全-存储器举例：(注3)】

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1、【VHDL程序举例大全-存储器举例：(注3)】--AFirst-inFirst-outMemory--afirst-infirstoutmemory,usesasynchronisingclock--genericsallowfifosofdifferentsizestobeinstantiatedlibraryIEEE;useIEEE.Std_logic_1164.all;entityFIFOMXNisgeneric(m,n:Positive:=8);--misfifodepth,nisfifowidthpor

2、t(RESET,WRREQ,RDREQ,CLOCK:inStd_logic;DATAIN:inStd_logic_vector((n-1)downto0);DATAOUT:outStd_logic_vector((n-1)downto0);FULL,EMPTY:inoutStd_logic);endFIFOMXN;architectureV2ofFIFOMXNistypeFifo_arrayisarray(0to(m-1))ofBit_vector((n-1)downto0);signalFifo_memory:

3、Fifo_array;signalWraddr,Rdaddr,Offset:Naturalrange0to(m-1);signalRdpulse,Wrpulse,Q1,Q2,Q3,Q4:Std_logic;signalDatabuffer:Bit_vector((n-1)downto0);begin--pulsesynchronisersforWRREQandRDREQ--modifiedforSynplifytoaprocesssync_ffs:processbeginwaituntilrising_edge(

4、CLOCK);Q1<=WRREQ;Q2<=Q1;Q3<=RDREQ;Q4<=Q3;endprocess;--concurrentlogictogeneratepulsesWrpulse<=Q2andnot(Q1);Rdpulse<=Q4andnot(Q3);Fifo_read:processbeginwaituntilrising_edge(CLOCK);ifRESET='1'thenRdaddr<=0;Databuffer<=(others=>'0');elsif(Rdpulse='1'andEMPTY='0'

5、)thenDatabuffer<=Fifo_memory(Rdaddr);Rdaddr<=(Rdaddr+1)modm;endif;endprocess;Fifo_write:processbeginwaituntilrising_edge(CLOCK);ifRESET='1'thenWraddr<=0;elsif(Wrpulse='1'andFULL='0')thenFifo_memory(Wraddr)<=To_Bitvector(DATAIN);Wraddr<=(Wraddr+1)modm;endif;en

6、dprocess;Offset<=(Wraddr-Rdaddr)when(Wraddr>Rdaddr)else(m-(Rdaddr-Wraddr))when(Rdaddr>Wraddr)else0;EMPTY<='1'when(Offset=0)else'0';FULL<='1'when(Offset=(m-1))else'0';DATAOUT<=To_Stdlogicvector(Databuffer)whenRDREQ='0'else(others=>'Z');endV2;