ARM7的体系结构介绍-外文翻译

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1、毕业设计(论文)外文资料翻译系别：电子信息系专业：通信工程班级：B100309姓名：张杨学号：B10030942外文出处：附件：1.原文；2.译文2014年03月AnIntroductiontotheARM7ArchitectureTrevorMartinCEng,MIEETechnicalDirectorThisarticlegivesanoverviewoftheARM7architectureandadescriptionofitsmajorfeaturesforadevelopernewtothedevice.Futu

2、rearticleswillexamineotheraspectsoftheARMarchitecture.BasicCharacteristicsTheprinciplefeatureoftheARM7microcontrolleristhatitisaregisterbasedload-and-storearchitecturewithanumberofoperatingmodes.WhiletheARM7isa32bitmicrocontroller,itisalsocapableofrunninga16-bitinst

3、ructionset,knownas"THUMB".Thishelpsitachieveagreatercodedensityandenhancedpowersaving.Whilealloftheregister-to-registerdataprocessinginstructionsaresingle-cycle,otherinstructionssuchasdatatransferinstructions,aremulti-cycle.Toincreasetheperformanceoftheseinstruction

4、s,theARM7hasathree-stagepipeline.Duetotheinherentsimplicityofthedesignandlowgatecount,ARM7istheindustryleaderinlow-powerprocessingonawattsperMIPbasis.Finally,toassistthedeveloper,theARMcorehasabuilt-inJTAGdebugportandon-chip"embeddedICE"thatallowsprogramstobedownloa

5、dedandfullydebuggedin-system.InordertokeeptheARM7bothsimpleandcost-effective,thecodeanddataregionsareaccessedviaasingledatabus.ThuswhiletheARM7iscapableofsingle-cycleexecutionofalldataprocessinginstructions,datatransferinstructionsmaytakeseveralcyclessincetheywillre

6、quireatleasttwoaccessesontothebus(onefortheinstructiononeforthedata).Inordertoimproveperformance,athreestagepipelineisusedthatallowsmultipleinstructionstobeprocessedsimultaneously.Thepipelinehasthreestages;FETCH,DECODEandEXECUTE.Thehardwareofeachstageisdesignedtobei

7、ndependentsouptothreeinstructionscanbeprocessedsimultaneously.Thepipelineismosteffectiveinspeedingupsequentialcode.Howeverabranchinstructionwillcausethepipelinetobeflushedmarringitsperformance.AsweshallseelatertheARM7designershadsomecleverideastosolvethisproblem.Fig

8、1ARM3-StagepipelineARM7ProgrammingModelTheprogrammer'smodeloftheARM7consistsof15userregisters,asshowninFig.3,withR15beingusedastheProgramC