6、is design uses the EP1K10TC100-1 chip to control CPU. The overall system uses the VHDL language. The 50MHZ crystal oscillator produces the clock pulse. The VHDL language obtains a second signal and other clock signal .Design frequency divider passes t
7、hrough the counter separately to the year, the month, Japan, divides, the second control logic accumulation to form the counting module, and makes the adjustment through the independent keyboard to the counting module to achieve the goal of adjusting
8、the time, and the system display output through 1602 liquid crystal. The system carries on the procedure software's translation, the simulation, the pin establishment, the bus interface and the disposition, downloading using the Quartus II sof
