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ID:1261755
大小:13.34 MB
页数:93页
时间:2017-11-09
《论文-基于fpga的电子密码锁的设计》由会员上传分享,免费在线阅读,更多相关内容在学术论文-天天文库。
1、,i.lfiFPGAFP7—8'8III,@W—FPGA@.IABSTRACTWiththedevelopmentofelectronictechnDloqy,electronicpasswordlockwithburglaralarmandotherfunctionsreplacinglesspasswordandpoorsecuritymechanicalcodelockisaninevitabletrend.comparedelectronicpasswordlockwithordinarymechanical
2、locks,ithasmanyuniqueadvantages:confidentiality,andsecurityinnature,donotusethekey,rememberpasswordcanunlockitetc.MostelectronicpasswordlocksweusednowisbaseduponSCMtechnology,SCMisitsmainlydevice,andthecreatingofencodinganddecodingdevicesisthefashionofSoftwarem
3、ode.Inpracticalapplication,thereliabilityofthesystemmaybeworsebecauseofeasyrunningflyDItheprogramme.ThispapermainlyexpatiatesadesignmethodofelectronicpasswordlockbaseduponFieldProgrammableGateArraydevice.WeuseFPGAdevicestocDnstructsystem,allofthealgorithmentire
4、lyachievedbythehardwarecircuit,becauseofFPGAhasthefunctionofISP,whenthedesignneedsIDbechangedWeonlyneedtochangethecontrolandinterfacecircuitofFPGA,EDAtoolsareusedtodownloadtheupdateddesigntoFPGAwithoutchangingthedesignoftheexternalcircuit,thisgreatlyenhancethee
5、fficiencyofthedesign.Therefore,weuseFPGAtoempolderthedigitalsystemhasnotonlyhighreliabilitybutalsoextremelycDnvenientofupgradingandimprovement.)nthispaper,weuseEDAtechnology,QuartusI)platformandhardwaredescriptionlanguagedesigninganelectronicpasswordlock,andita
6、chievedthroughanFPGAchip.Keywords:electronicpasswordlock;FPGA;hardwaredescriptionlanguage;EDA.72.1FPGA82.33.3@(TOP284,z0AI3oŒft%PŒT,Y›sx,n7、NT>=NTL,gfTr>TEN,gJ1.2.28&W%):%:%FN)!@NT%*'J'é4R,%J?hDQ*x9.(2)lb8#•NT3=a(a-1):.:.3,4,10,12,14,16.NT4•æ?I¢834YJ?ßÜ€/6YÜ3B‹BY'æ6Y4¢BBB%EI?J¥=ßL4zoxixnøe‹,es«GAL.GALEPLDg)ss)$@,@FPGA@gg($(FPGA)V,FPGA207&U6seX1t7/'sicB¥6,8aJ€xJaB66&5aP2P«Bét/J•fb2.2.1FPGAFPGA.FPF8、PGASRAM@IOBXilinxSpartan-D[6](seAM›ssas,BJiC6Bse»MBIG»o48śBa,?tSRAM@IżTjB%iJG-*i°CLB.łOB@@PI@§g91?łM2%BdRśś£KS.,?>hRSBTf3°%Agg.LCA@@]&lXACT(XilinxAutomatedCAETools)CLB2.1CL
7、NT>=NTL,gfTr>TEN,gJ1.2.28&W%):%:%FN)!@NT%*'J'é4R,%J?hDQ*x9.(2)lb8#•NT3=a(a-1):.:.3,4,10,12,14,16.NT4•æ?I¢834YJ?ßÜ€/6YÜ3B‹BY'æ6Y4¢BBB%EI?J¥=ßL4zoxixnøe‹,es«GAL.GALEPLDg)ss)$@,@FPGA@gg($(FPGA)V,FPGA207&U6seX1t7/'sicB¥6,8aJ€xJaB66&5aP2P«Bét/J•fb2.2.1FPGAFPGA.FPF
8、PGASRAM@IOBXilinxSpartan-D[6](seAM›ssas,BJiC6Bse»MBIG»o48śBa,?tSRAM@IżTjB%iJG-*i°CLB.łOB@@PI@§g91?łM2%BdRśś£KS.,?>hRSBTf3°%Agg.LCA@@]&lXACT(XilinxAutomatedCAETools)CLB2.1CL
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