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1、IEEEStandardforSystemVerilog—UnifiedHardwareDesign,Specification,andVerificationLanguageIEEEComputerSocietyandtheIEEEStandardsAssociationCorporateAdvisoryGroupSponsoredbytheDesignAutomationStandardsCommitteeIEEEIEEEStd1800™-20123ParkAvenue(RevisionofNewYork,NY10016-5997IE
2、EEStd1800-2009)USA21February2013IEEEStd1800™-2012(RevisionofIEEEStd1800-2009)IEEEStandardforSystemVerilog—UnifiedHardwareDesign,Specification,andVerificationLanguageSponsorDesignAutomationStandardsCommitteeoftheIEEEComputerSocietyandtheIEEEStandardsAssociationCorporateAdv
3、isoryGroupApproved5December2012IEEE-SAStandardsBoardAbstract:ThedefinitionofthelanguagesyntaxandsemanticsforSystemVerilog,whichisaunifiedhardwaredesign,specification,andverificationlanguage,isprovided.Thisstandardincludessupportformodelinghardwareatthebehavioral,registert
4、ransferlevel(RTL),andgate-levelabstractionlevels,andforwritingtestbenchesusingcoverage,assertions,object-orientedprogramming,andconstrainedrandomverification.Thestandardalsoprovidesapplicationprogramminginterfaces(APIs)toforeignprogramminglanguages.Keywords:assertions,des
5、ignautomation,designverification,hardwaredescriptionlanguage,HDL,HDVL,IEEE1800™,PLI,programminglanguageinterface,SystemVerilog,Verilog®,VPITheInstituteofElectricalandElectronicsEngineers,Inc.3ParkAvenue,NewYork,NY10016-5997,USACopyright©2013byTheInstituteofElectricalandEl
6、ectronicsEngineers,Inc.Allrightsreserved.Published21February2013.PrintedintheUnitedStatesofAmerica.IEEE,802,andPOSIXareregisteredtrademarksintheU.S.Patent&TrademarkOffice,ownedbyTheInstituteofElectricalandElectronicsEngineers,Incorporated.VerilogisaregisteredtrademarkofCa
7、denceDesignSystems,Inc.PDF:ISBN978-0-7381-8110-3STDGT98078Print:ISBN978-0-7381-8111-0STDPD98078IEEEprohibitsdiscrimination,harassmentandbullying.Formoreinformation,visithttp://www.ieee.org/web/aboutus/whatis/policies/p9-26.html.Nopartofthispublicationmaybereproducedinanyf
8、orm,inanelectronicretrievalsystemorotherwise,withoutthepriorwrittenpermissionofthepublisher.Noti
