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ID:11364960
大小:57.00 KB
页数:6页
时间:2018-07-11
《adc0809-vhdl程序并显示》由会员上传分享,免费在线阅读,更多相关内容在教育资源-天天文库。
1、--编程软件:ISE10.1--10年北京市电设比赛准备程序,调了半天的程序,绝对能用,但是说不考了--后面有引脚配置代码--程序libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entityadcokisPORT(D:INSTD_LOGIC_VECTOR(7DOWNTO0);CLK,EOC:INSTD_LOGIC;ALE,START,OE:OUTSTD_LOGIC;ADDA:OUTSTD_L
2、OGIC_VECTOR(2DOWNTO0);Q:OUTSTD_LOGIC_VECTOR(7DOWNTO0);clockout:outstd_logic;seg7:outSTD_LOGIC_VECTOR(6downto0);an:outSTD_LOGIC_VECTOR(3downto0);dp:outSTD_LOGIC);endadcok;architectureBehavioralofadcokisTYPESTATESIS(ST0,ST1,ST2,ST3,ST4,ST5,ST6,ST7);SIGNALCURRENT_STATE,NEXT
3、_STATE:STATES:=ST0;SIGNALREGL:STD_LOGIC_VECTOR(7DOWNTO0);SIGNALREG:STD_LOGIC_VECTOR(15DOWNTO0):="0000000000000000";SIGNALLOCK:STD_LOGIC;signalcclk,clkseg:std_logic;signals:std_logic_vector(1downto0):="00";signaldigit:std_logic_vector(3downto0);signalaen:std_logic_vector(
4、3downto0);signalqat,qbt,qct,qdt:STD_LOGIC_VECTOR(3downto0);signalb:STD_LOGIC_VECTOR(13downto0):="00000000000000";signalp:STD_LOGIC_VECTOR(16downto0):="00000000000000000";beginADDA<="000";--LOCK1<=LOCK;clockout<=cclk;REG(7DOWNTO0)<=REGL;Q<=REGL;dp<='0';aen(0)<=qdt(3)orqdt
5、(2)orqdt(1)orqdt(0);aen(1)<=qdt(3)orqdt(2)orqdt(1)orqdt(0)orqct(3)orqct(2)orqct(1)orqct(0);aen(2)<=qdt(3)orqdt(2)orqdt(1)orqdt(0)orqct(3)orqct(2)orqct(1)orqct(0)orqbt(3)orqbt(2)orqbt(1)orqbt(0);aen(3)<='1';b(7downto0)<=REGL(7DOWNTO0);-------------------------------------
6、-----qat<=P(3downto0);qbt<=P(7downto4);qct<=P(11downto8);qdt<="0000";------------------------------------------process(b)variablez:std_logic_vector(32downto0);beginforiin0to32loopz(i):='0';endloop;z(16downto3):=b;forjin0to10loopif(z(17downto14)>"0100")thenz(17downto14):=
7、z(17downto14)+"0011";endif;if(z(21downto18)>"0100")thenz(21downto18):=z(21downto18)+"0011";endif;if(z(25downto22)>"0100")thenz(25downto22):=z(25downto22)+"0011";endif;if(z(29downto26)>"0100")thenz(29downto26):=z(29downto26)+"0011";endif;z(32downto1):=z(31downto0);endloop
8、;p<=z(30downto14);endprocess;PROCESS(CLK)VARIABLEq:INTEGER:=0;BEGINIFCLK'EVENTANDCLK='1'THENq:=q+1;IFq<
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