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1、常见的并行语句有：l进程语句l块语句l并行信号赋值语句l并行过程调用语句l元件例化语句l生成语句l并行断言语句1、进程语句举例LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYd_ffISPORT(clk,d:INSTD_LOGIC;q:OUTSTD_LOGIC);ENDd_ff;ARCHITECTUREmy_archOFd_ffISBEGINPROCESS(clk)BEGINIFclk'EVENTANDclk='1'THENq<=d;ENDIF;ENDPROCESS;ENDmy_arch;2、块语句举例l多个BLOCK
2、ENTITYcpuISPORT(clk,interrupt:INSTD_LOGIC;addr:OUTtw32; data:INOUTtw32);ENDcpu;ARCHITECTUREcpu_blkOFcpuISSIGNALibus,dbus:tw32;BEGINALU:BLOCKSIGNALqbus:tw32;BEGIN……--并行处理语句ENDBLOCKALU;REG8:BLOCKSIGNALzbus:tw32;BEGIN……--并行处理语句ENDBLOCKREG8;ENDcpu_blk;l嵌套BLOCKb1:BLOCKSIGNALs:BIT;--BLOCK
3、b1中s的说明BEGINs<=aANDb;--s来自b1b2:BLOCKSIGNALs1:BIT;--BLOCKb2中s1的说明BEGINs1<=cANDd;--s1来自b2b3:BLOCKBEGINz<=s;--s来自b1ENDBLOCKb3;ENDBLOCKb2;y<=s;--s来自b1ENDBLOCKb1;3、条件信号赋值语句应用举例四选一数据选择器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYmux4ISPORT(i0,i1,i2,i3,a,b:INSTD_LOGIC;q:OUTSTD_LOGIC);ENDm
4、ux4;ARCHITECTUREarch1OFmux4ISSIGANLsel:STD_LOGIC_VECTOR(1DOWNTO0);BEGINsel<=a&b;q<=i0WHENsel="00"ELSEi1WHENsel="01"ELSEi2WHENsel="10"ELSEi3WHENsel="11"ELSE'X';ENDarch1;4、选择信号赋值语句应用举例四选一数据选择器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYmux4ISPORT(i0,i1,i2,i3,a,b:INSTD_LOGIC;q:OUTSTD_
5、LOGIC);ENDmux4;ARCHITECTUREarch2OFmux4ISSIGANLsel:STD_LOGIC_VECTOR(1DOWNTO0);BEGINsel<=a&b;WITHselSELECTq<=i0WHEN"00",i1WHEN"01",i2WHEN"10",i3WHEN"11",'X'WHENOTHERS;ENDarch2;5、元件例化语句应用举例1）设计好2输入的与门，名为and2_1LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYand2_1ISPORT(a,b:INBIT;c:OUTBIT)
6、;ENDand2_1;ARCHITECTURErtlOFand2_1ISBEGINc<=aANDb;ENDrtl;2）利用设计好的两输入与门，通过元件例化语句，构造一个三输入的与门LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYand3_1ISPORT(a,b,c:INBIT;d:OUTBIT);ENDand3_1;ARCHITECTUREstrOFand3_1ISCOMPONENTand2_1ISPORT(a,b:INBIT;c:OUTBIT);ENDCOMPONENT;SINGALs:BIT;BEGINu1:and
7、2_1PORTMAP(a=>a,b=>b,c=>s);u2:and2_1PORTMAP(s,c,d);ENDstr;6、生成语句举例例1ARCHITECTURExx_aOFxxISCOMPONENTcompISPORT(x:INBIT;y:OUTBIT);ENDCOMPONENT;SIGNALa,b:BIT_VECTOR(0TO7);BEGINgen:FORiIN0TO7GENERATElh:compPORTMAP(x=>a(i),y=>b(i));ENDGENERATEgen;ENDxx_a;例2移位寄存器1)先设计1位D触发器d_ffLIBRARYIEEE
8、;USEIEEE.STD_LOGIC_
