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1、Verilog音乐播放器1、音符对照表http://wenku.baidu.com/link?url=Oax-aXOjWdo-tES0iGNkpxGpVP0OhEL-Xm42WIvqvUhQ6NNAs96MmOyANcHu6FzUhDCWZ1jyBtk2yDCxPSPID750t4zb3JR4UqhtWebECOS2、顶层结构3、代码3.1、顶层代码：modulemusicplayer_1(clk,reset,Q);inputclk;inputreset;outputQ;//----------------------------------------wirecl
2、k_MHz;wireclk_4Hz;wire[5:0]Index;//64geyinfuwire[10:0]Tone;//2048//----------------------------------------clkMHzu1(clk,reset,clk_MHz);//baochiqianhoushunxuyizhiclk4Hzu2(clk,reset,clk_4Hz);notetabu3(clk_4Hz,reset,Index);romu4(Index,clk,Tone);singoutu5(clk_MHz,reset,Tone,Q);endmodule3.2
3、、U1代码moduleclkMHz(clk,reset,clk_MHz);//baochiqianhoushunxuyizhiinputclk;inputreset;outputclk_MHz;//----------------------------------------------reg[5:0]Q1;regclk_MHz_1;always@(posedgeclkornegedgereset)beginif(!reset)Q1<=6'd0;//Asy_rstelseif(Q1<6'd63)Q1<=Q1+1'b1;//0~6364circleelseQ1<=5
4、'd0;end//------------------------------------------------------------------------always@(posedgeclkornegedgereset)beginif(!reset)clk_MHz_1<=1'b1;//zhiningelseif(Q1==6'd63)clk_MHz_1<=~clk_MHz_1;end//-------------------------------------------------------------------------assignclk_MHz=c
5、lk_MHz_1;endmodule3.3、U2代码moduleclk4Hz(clk,reset,clk_4Hz);inputclk;inputreset;outputclk_4Hz;//--------------------------------------reg[21:0]Q2;regclk_4Hz_1;always@(posedgeclkornegedgereset)beginif(!reset)Q2<=22'd0;//Asy_rstelseif(Q2<22'd2499999)Q2<=Q2+1'b1;//0~9999999circleelseQ2<=22'
6、d0;end//------------------------------------------------------------------------always@(posedgeclkornegedgereset)beginif(!reset)clk_4Hz_1<=1'b1;//zhiningelseif(Q2==22'd2499999)clk_4Hz_1<=~clk_4Hz_1;end//-------------------------------------------------------------------------assignclk_
7、4Hz=clk_4Hz_1;endmodule3.4、U3代码modulenotetab(clk_4Hz,reset,Index);inputclk_4Hz;inputreset;output[5:0]Index;//--------------------------------------------reg[5:0]W;always@(posedgeclk_4Hzornegedgereset)//sixteencirclebeginif(!reset)W<=6'd0;elseif(W<6'd63)W<=W+1'b1;//[0-63]sum64elseW<=6
