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ID:6807343
大小:902.00 KB
页数:57页
时间:2018-01-26
《多周期mpis指令集设计》由会员上传分享,免费在线阅读,更多相关内容在工程资料-天天文库。
1、指令类型[31:26][25:21][20:16][15:11][10:6][5:0]R类型OpRsRtRdshamtfunct含义nop00000000000000000000空操作addursrtrd00000加(不带溢出)subursrtrd00000减(不带溢出)andrsrtrd00000与orrsrtrd00000或xorrsrtrd00000异或norrsrtrd00000或非sllvrsrtrd00000逻辑左移变量srlvrsrtrd00000逻辑右移变量I类型OpRsRtimmediate
2、bltzrs00000Immediate小于0转移beqrsrtImmediate相等转移bnersrtImmediate不相等转移addirsrtImmediate加立即数andirsrtImmediate与立即数orirsrtImmediate或立即数lwrsrtImmediate取字swrtrtImmediate存字J类型OpAddressjaddress无条件跳转综述:本设计选用了如下指令,基于此设计出了单周期MIPS处理器,并在单周期的基础上添加了5级流水线设计出了带五级流水线的MIPS处理器。第一
3、部分单周期MIPS处理器一、代码------------------------------------------------------------------------------------ModuleName:top_mips-Behavioral顶层模块----------------------------------------------------------------------------------libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;us
4、eIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entitytop_mipsisport(reset:instd_logic;clk:instd_logic;ov:outstd_logic);endtop_mips;architectureBehavioraloftop_mipsissignals_pc:std_logic_vector(31downto0);---pc输入signals_pc_i:std_logic_vector(31down
5、to0);---pc输出signals_command:std_logic_vector(31downto0);---指令signals_add1_pc:std_logic_vector(31downto0);---pc+1值signals_shift:std_logic_vector(27downto0);--指令低26位左移2位后值signals_jump_pc:std_logic_vector(31downto0);--绝对跳转signals_regdst:std_logic;----控制信号signa
6、ls_jump:std_logic;signals_branch:std_logic;signals_memread:std_logic;signals_memtoreg:std_logic;signals_aluop:std_logic_vector(3downto0);signals_memwrite:std_logic;signals_alusrc:std_logic;signals_regwrite:std_logic;signals_opa:std_logic_vector(31downto0);-
7、---ALU操作数signals_opb:std_logic_vector(31downto0);----ALU操作数signals_reg_data:std_logic_vector(31downto0);--寄存器读出的第二个数据signals_imm_data:std_logic_vector(31downto0);---低16位符号扩展后signals_zero:std_logic;signals_alu_result:std_logic_vector(31downto0);signals_branc
8、h_pc:std_logic_vector(31downto0);----条件跳转signals_1orbranch:std_logic_vector(31downto0);signals_ram_data:std_logic_vector(31downto0);signals_wr_data:std_logic_vector(31downto0);signals_mux:std_logic;sig
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