数字集成电路第七章培训讲学.ppt

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1、数字集成电路第七章NamingConventionsInourtext:alatchislevelsensitivearegisterisedge-triggeredTherearemanydifferentnamingconventionsForinstance,manybookscalledge-triggeredelementsflip-flopsThisleadstoconfusionhoweverLatchversusRegisterLatchstoresdatawhenclockislowDClkQDClkQRegisterstoresdatawhenclockrise

2、sClkClkDDQQLatchesLatch-BasedDesignNlatchistransparentwhenf=0Platchistransparentwhenf=1NLatchLogicLogicPLatchfTimingDefinitionstCLKtDtc2qtholdtsutQDATASTABLEDATASTABLERegisterCLKDQCharacterizingTimingRegisterLatchMaximumClockFrequencyAlso:tcdreg+tcdlogic>tholdtcd:contaminationdelay=minimumdela

3、ytclk-Q+tp,comb+tsetup=TPositiveFeedback:Bi-StabilityVo1Vi25Vo1Vi25Vo1Vi1ACBVo2Vi1=Vo2Vo1Vi2Vi2=Vo1Meta-StabilityGainshouldbelargerthan1inthetransitionregionWritingintoaStaticLatchDCLKCLKDConvertingintoaMUXForcingthestate(canimplementasNMOS-only)Usetheclockasadecouplingsignal,thatdistinguishesb

4、etweenthetransparentandopaquestatesMux-BasedLatchesNegativelatch(transparentwhenCLK=0)Positivelatch(transparentwhenCLK=1)CLK10DQ0CLK1DQMux-BasedLatchMux-BasedLatchNMOSonlyNon-overlappingclocksMaster-Slave(Edge-Triggered)RegisterTwooppositelatchestriggeronedgeAlsocalledmaster-slavelatchpairMaster

5、-SlaveRegisterMultiplexer-basedlatchpairClk-QDelaySetupTimeReducedClockLoadMaster-SlaveRegisterAvoidingClockOverlapCLKCLKAB(a)Schematicdiagram(b)OverlappingclockpairsXDQCLKCLKCLKCLKOverpoweringtheFeedbackLoop─Cross-CoupledPairsNOR-basedset-resetCross-CoupledNANDCross-coupledNANDsAddedclockThis

6、isnotusedindatapathsanymore,butisabasicbuildingmemorycellSizingIssuesOutputvoltagedependenceontransistorwidthTransientresponseStorageMechanismsDCLKCLKQDynamic(charge-based)StaticMakingaDynamicLatchPseudo-StaticMorePreciseSetupTimeSetup/HoldTimeIllustrationsCircuitbeforeclockarrival(Setup-1case

7、)Setup/HoldTimeIllustrationsCircuitbeforeclockarrival(Setup-1case)Setup/HoldTimeIllustrationsCircuitbeforeclockarrival(Setup-1case)Setup/HoldTimeIllustrationsCircuitbeforeclockarrival(Setup-1case)Setup/HoldTimeIllustrationsC