数字钟电路原理图程序.doc

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1、数字钟电路原理图程序清单********顶层程序描述***********程序：TIMER_SET.VHDlibraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entitytimer_setisport(cp:instd_logic;--CLOCKsegout:outstd_logic_vector(7downto0);--SEG7DISPLAYO/Pselout:outstd_logic_vector(5downto0);--SELECTSEG7O/

2、Pnumout:outstd_logic_vector(3downto0);--NUMBERDISPLAYSIGNALkey:instd_logic_vector(2downto0));--TIMER&ADJUST&CLRendtimer_set;architecturebehavioraloftimer_setiscomponentcounter60port(cp:instd_logic;bin:outstd_logic_vector(5downto0);s:instd_logic;clr:instd_logic;ec:instd_logic;cy60:outstd_logic);endc

3、omponent;componentcounter24port(cp:instd_logic;bin:outstd_logic_vector(5downto0);s:instd_logic;clr:instd_logic;ec:instd_logic;cy24:outstd_logic);endcomponent;componentfree_counterport(cp:instd_logic;dbs:instd_logic_vector(5downto0);dbm:instd_logic_vector(5downto0);dbh:instd_logic_vector(5downto0);s

4、tate:instd_logic_vector(1downto0);sec:outstd_logic;sample:outstd_logic;glitter:outstd_logic;bin:outstd_logic_vector(5downto0);enb:outstd_logic_vector(2downto0);sel:outstd_logic_vector(5downto0);match:outstd_logic;s:outstd_logic_vector(2downto0));endcomponent;componentbinary_bcdport(bin:instd_logic_

5、vector(5downto0);bcd:outstd_logic_vector(7downto0));endcomponent;componentseven_segmentport(num:instd_logic_vector(3downto0);seg:outstd_logic_vector(6downto0));endcomponent;componentdebounceport(cp:instd_logic;sample:instd_logic;key:instd_logic_vector(2downto0);dly_out:outstd_logic);endcomponent;co

6、mponentdifferentialport(cp:instd_logic;dly_out:instd_logic;diff:outstd_logic);endcomponent;componenttimersetport(cp:instd_logic;diff:instd_logic;key:instd_logic_vector(2downto0);state:outstd_logic_vector(1downto0));endcomponent;signalbin:std_logic_vector(5downto0);--BINARYO/Psignaldbs:std_logic_vec

7、tor(5downto0);--BINARYSECO/Psignaldbm:std_logic_vector(5downto0);--BINARYMINO/Psignaldbh:std_logic_vector(5downto0);--BINARYHRO/Psignalenb:std_logic_vector(2downto0);--ENABLEHR&MIN&SECO/Psignalsec:std_logic