外文翻译排版格式参考.doc

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1、毕业设计(论文)外文资料翻译系别：电子信息系专业：通信工程班级：B100309姓名：张杨学号：B10030942外文出处：附件：1.原文；2.译文2014年03月AnIntroductiontotheARM7ArchitectureTrevorMartinCEng,MIEETechnicalDirectorThisarticlegivesanoverviewoftheARM7architectureandadescriptionofitsmajorfeaturesforadevelopernewtothedevice.Futurearti

2、cleswillexamineotheraspectsoftheARMarchitecture.BasicCharacteristicsTheprinciplefeatureoftheARM7microcontrolleristhatitisaregisterbasedload-and-storearchitecturewithanumberofoperatingmodes.WhiletheARM7isa32bitmicrocontroller,itisalsocapableofrunninga16-bitinstructionset,k

3、nownas"THUMB".Thishelpsitachieveagreatercodedensityandenhancedpowersaving.Whilealloftheregister-to-registerdataprocessinginstructionsaresingle-cycle,otherinstructionssuchasdatatransferinstructions,aremulti-cycle.Toincreasetheperformanceoftheseinstructions,theARM7hasathree

4、-stagepipeline.Duetotheinherentsimplicityofthedesignandlowgatecount,ARM7istheindustryleaderinlow-powerprocessingonawattsperMIPbasis.Finally,toassistthedeveloper,theARMcorehasabuilt-inJTAGdebugportandon-chip"embeddedICE"thatallowsprogramstobedownloadedandfullydebuggedin-sy

5、stem.InordertokeeptheARM7bothsimpleandcost-effective,thecodeanddataregionsareaccessedviaasingledatabus.ThuswhiletheARM7iscapableofsingle-cycleexecutionofalldataprocessinginstructions,datatransferinstructionsmaytakeseveralcyclessincetheywillrequireatleasttwoaccessesontothe

6、bus(onefortheinstructiononeforthedata).Inordertoimproveperformance,athreestagepipelineisusedthatallowsmultipleinstructionstobeprocessedsimultaneously.Thepipelinehasthreestages;FETCH,DECODEandEXECUTE.Thehardwareofeachstageisdesignedtobeindependentsouptothreeinstructionscan

7、beprocessedsimultaneously.Thepipelineismosteffectiveinspeedingupsequentialcode.Howeverabranchinstructionwillcausethepipelinetobeflushedmarringitsperformance.AsweshallseelatertheARM7designershadsomecleverideastosolvethisproblem.Fig1ARM3-StagepipelineARM7ProgrammingModelThe

8、programmer'smodeloftheARM7consistsof15userregisters,asshowninFig.3,withR15beingusedastheProgramC