tutorial_quartusii_intro_vhdl.pdf

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1、Quartus®IIIntroductionforVHDLUsersThistutorialpresentsanintroductiontotheQuartus®IIsoftware.ItgivesageneraloverviewofatypicalCADflowfordesigningcircuitsthatareimplementedbyusingFPGAdevices,andshowshowthisflowisrealizedintheQuartus®IIsoftware.Thedesignprocessisillustratedbygi

2、vingstep-by-stepinstructionsforusingtheQuartus®IIsoftwaretoimplementasimplecircuitinanAltera®FPGAdevice.TheQuartus®IIsystemincludesfullsupportforallofthepopularmethodsofenteringadescriptionofthedesiredcircuitintoaCADsystem.ThistutorialmakesuseoftheVHDLdesignentrymethod,inw

3、hichtheuserspecifiesthedesiredcircuitintheVHDLhardwaredescriptionlanguage.AnotherversionofthistutorialisavailablethatusesVeriloghardwaredescriptionlanguage.ThescreencapturesinthetutorialwereobtainedusingQuartus®IIversion9.0;ifotherversionsofthesoft-wareareused,someoftheimag

4、esmaybeslightlydifferent.Contents:GettingStartedStartingaNewProjectDesignEntryUsingVHDLCodeCompilingtheVHDLCodeUsingtheRTLViewerSpecifyingTimingContraintsQuartus®IIWindowsComputerAidedDesign(CAD)softwaremakesiteasytoimplementadesiredlogiccircuitbyusingapro-grammablelogicde

5、vice,suchasafield-programmablegatearray(FPGA)chip.AtypicalFPGACADflowisillustratedinFigure1.DesignEntrySynthesisFunctionalSimulationNoDesigncorrect?YesFittingTimingAnalysisandSimulationNoTimingrequirementsmet?YesProgrammingandConfigurationFigure1:TypicalCADflow.Itinvolvesthef

6、ollowingbasicsteps:•DesignEntry–thedesiredcircuitisspecifiedeitherbyusingahardwaredescriptionlanguage,suchasVerilogorVHDL,orbymeansofaschematicdiagram•Synthesis–theCADSynthesistoolsynthesizesthecircuitintoanetlistthatgivesthelogicelements(LEs)neededtorealizethecircuitandthe

7、connectionsbetweentheLEs•FunctionalSimulation–thesynthesizedcircuitistestedtoverifyitsfunctionalcorrectness;thesimulationdoesnottakeintoaccountanytimingissues•Fitting–theCADFittertooldeterminestheplacementoftheLEsdefinedinthenetlistintotheLEsinanactualFPGAchip;italsochooses

8、routingwiresinthechiptomaketherequiredconnectionsbetweenspecificLEs•TimingAnalysis–propaga