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时间:2019-11-26
《基于IP核的PCIE总线接口逻辑的设计和实现》由会员上传分享,免费在线阅读,更多相关内容在学术论文-天天文库。
1、Õ47ÖÕ1×!"ØÙÚÛVol.47No.12017Ü1ÝAeronauticalComputingTechniqueJan.2017O]IP´WPCIEÇ'¹×ØWÖÔ>Z¶ÙÚ,$ó,EÛ(6-[m"*-.no(p<=>,!""*710068)01:Ü%PCIE}«>?,ÓìÛX,ÿZ,)[×ÝÞSPCIE}«_Ïe*,%`dEFIP¿*<=,QXilinxVirtex-7ßFPGAUáâ@PCIE}«[×ÝÞ*,)S,£>?@Ïee.,·¿ÝÞek&:>?àì4á³DMA¬,mDMA¬öe©PCIE}«ö*70%áU。234:IP¿;PCIE;FPGA;[×ÝÞ;D
2、MA56789:TN915.851:;<=>:A:?@9:1671?654X(2017)01?0116?05DesigningandImplementationBasedonIPCoreofInterfaceLogicforPCIExpressPUKai,TANGQing,TIANYuan(Xi′anAeronauticsComputingTechniqueResearchInstitute,AVIC,Xi′an710068,China)Abstract:WhenPCIEisusedforinterconnectionofdevices,theinterfacelogicis
3、neededforinteractionbetweenthebusandinternalfunction.ThispaperadoptedamethodbasedonIPcore,andcompletedthedesigningandimplementationoftheinterfacelogicinXilinxVirtex-7seriesFPGA.Thenthefunctionandperformancewasverified.TheresultsshowedthatregistersaccessinganddatatransferinDMAmodewerecorrect
4、lyandthebandwidthofDMAtransmissionwasmorethan70%.Keywords:IPCore;PCIE;FPGA;interfacelogic;DMAAB³&euy,ów·nPCIEóô¾CÏÊ[1-2]M$3ôY。e+U3)îâC35、kåÖz¸8¸,wÛ3¸÷_¸¾3P@[3]ó3m·,Ë®ePCI376、ÚÛ_deøv¸{j,{7、_ß÷uøv¸3¸2002ÜoIntel,8þ¦·HÕÉ8、,=ó3å¾@5n=üý。ié19、32.5GbpskH310、38Gbps,_PC¸¾P,FmtPä師!;TypeP<9}!ì#&11、5Høõ³-,txeCPUe¥bäå¸wÛ;TCPäåó3wÛ;TDPe=[4-5]°:m3Ð:mB,jPCIEmBYZ®eb>;EPPe>6;AttrPäåks;ATPä¿3´ÀâCePCIE°3«:,;³´ÀâCåÝÉwÛ;LengthPäå12、e=63³&w·;ePCIE}ó3u®,uM¥b¿3âC3®-。LastDWBEPäåQ¥35,C;1stDW[6][7]:~13、Xilinx7GFPGAH3PCIE¡¯eBEPäåÕQ¥35,C;AddressPäå,bØPCIEmBYZ,NfPCIEÝÉ;Com14、pleterIDPäåðID;Compl.Status5N3âC,Ü'(ePCIEç5N3HÓPäåOë;BCMPäåâÇ35Ø;CÏ,Üe3t67yzsCu%,uo-ByteCountPäå5Ø;LowerAddressPäPCIE®emB3ST>¦V»¢。åE6ÝÉ。1PCIEÙÁ2×ØÞ±ÖÔ-15、V:@A(1985-),Ç,ÈÉع,u_«,uåÎÏ,Ð>ÑÒ6ÓeHÓÚÛ<óU©FPGAbØÚÛ。2017Ü1Ý@AQ:pIP¯3PCIEmBYZ3bØ8Nf·117·:bؤ2>NfPCIEU£@3âC¥,¦©¦T.,¦TmBÎÊ=F{¦TmBÍR>PCIEe-16、PCIE¡¯e3,Ü_e-
5、kåÖz¸8¸,wÛ3¸÷_¸¾3P@[3]ó3m·,Ë®ePCI37
6、ÚÛ_deøv¸{j,{
7、_ß÷uøv¸3¸2002ÜoIntel,8þ¦·HÕÉ
8、,=ó3å¾@5n=üý。ié1
9、32.5GbpskH3
10、38Gbps,_PC¸¾P,FmtPä師!;TypeP<9}!ì#&
11、5Høõ³-,txeCPUe¥bäå¸wÛ;TCPäåó3wÛ;TDPe=[4-5]°:m3Ð:mB,jPCIEmBYZ®eb>;EPPe>6;AttrPäåks;ATPä¿3´ÀâCePCIE°3«:,;³´ÀâCåÝÉwÛ;LengthPäå
12、e=63³&w·;ePCIE}ó3u®,uM¥b¿3âC3®-。LastDWBEPäåQ¥35,C;1stDW[6][7]:~
13、Xilinx7GFPGAH3PCIE¡¯eBEPäåÕQ¥35,C;AddressPäå,bØPCIEmBYZ,NfPCIEÝÉ;Com
14、pleterIDPäåðID;Compl.Status5N3âC,Ü'(ePCIEç5N3HÓPäåOë;BCMPäåâÇ35Ø;CÏ,Üe3t67yzsCu%,uo-ByteCountPäå5Ø;LowerAddressPäPCIE®emB3ST>¦V»¢。åE6ÝÉ。1PCIEÙÁ2×ØÞ±ÖÔ-15、V:@A(1985-),Ç,ÈÉع,u_«,uåÎÏ,Ð>ÑÒ6ÓeHÓÚÛ<óU©FPGAbØÚÛ。2017Ü1Ý@AQ:pIP¯3PCIEmBYZ3bØ8Nf·117·:bؤ2>NfPCIEU£@3âC¥,¦©¦T.,¦TmBÎÊ=F{¦TmBÍR>PCIEe-16、PCIE¡¯e3,Ü_e-
15、V:@A(1985-),Ç,ÈÉع,u_«,uåÎÏ,Ð>ÑÒ6ÓeHÓÚÛ<óU©FPGAbØÚÛ。2017Ü1Ý@AQ:pIP¯3PCIEmBYZ3bØ8Nf·117·:bؤ2>NfPCIEU£@3âC¥,¦©¦T.,¦TmBÎÊ=F{¦TmBÍR>PCIEe-16、PCIE¡¯e3,Ü_e-
16、PCIE¡¯e3,Ü_e-
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