第三章EDA工具

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1、第三章SoC设计与EDA工具OutlinesIntroductionESLDesignToolEDAforCell-basedDesignDynamic&StaticVerificationSynthesisDesignforTestingPlace&RoutePhysicalChecking/ExtractionEDACompaniesandToolsEDAMarketGlobalIncomeofEDAMarketSource:GartnerDataquestTrendsofEDATools:RTL,GLan

2、dESLSource:GartnerDataquestSource:SynopsysMiniDAC04DesignTechnologyNeedsasGeometriesShrinkSource:SynopsysDesignTechnologyNeedsasGeometriesShrink–cont.Tool,AutomationandMethodsAutomationisnotintendedtoreplacepeoplenorisitintendedtoturnpeopleinautomationsToold

3、evelopmentcannotoperateindependentlyfromthedevelopmentofdesignmethodologiesToolsarenotmethodsItisimpossibletodevelop“plug&Play”toolsToolshaveashelf-life.Don’ttrytomakethemlastforever.FocusonmethodologiesOutlinesIntroductionESLDesignToolEDAforCell-basedDesign

4、Dynamic&StaticVerificationSynthesisDesignforTestingPlace&RoutePhysicalChecking/ExtractionOverviewofEDACompaniesandToolsESLDesignWhatisESLdesignUsinghigh-levelmodelingandsimulationtechniquestocreatean“executablespecification”ofthedesignora“virtualplatform”.ES

5、LhardwaredesigntoolsutilizeindustrystandardlanguagesfortransactionlevelmodelingC/C++,SystemC,SystemVerilogTrend:ESLarithmeticsynthesistoolESL–HighAbstractionLevelLayoutSignals&GatesVerilogVHDLHW/SWCo-VerificationRTLVerificationTransactionsSystemCSystemVerilo

6、gArchitectureExplorationBenchmarkingSWDevelopmentESLAlgorithmDesignMatlabFunctionCallsESLDesignESLdesignenabling:System-leveldesignPre-siliconembeddedsoftwaredesignHW/SWco-designArchitectureexplorationVirtualprototypingCo-simulation/co-verificationProgrammab

7、leLanguageforESLDesignUsehighlevellanguagetobuildmodulesC/C++eProgrammbleLanguageSystemCSystemVerilogRequirementofSimulationEnvironmentAccuracy:highabstractionmodel,exampleusingSystemC,shouldbecycle-orpinaccuratePerformance:fastenoughtorunRTOSUsage:forbothSW

8、andHWteamsAvailability:availableearlyinthedesigncycletomeettime-to-market,HW/SWco-design,co-verificationOutlinesIntroductionESLDesignToolEDAforCell-basedDesignDynamic&StaticVerificationSynthesis