Chisel constructing hardware in a Scala Embedded Language-dac2012

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1、Chisel:ConstructingHardwareinaScalaEmbeddedLanguageJonathanBachrach,HuyVo,BrianRichards,YunsupLee,AndrewWaterman,RimasAvižienis,JohnWawrzynek,KrsteAsanovic´EECSDepartment,UCBerkeley{jrb

2、huytbvo

3、richards

4、yunsup

5、waterman

6、rimas

7、johnw

8、krste}@eecs.berkeley.eduABST

9、RACTdesignsmustbeinferredfromasubsetofthelanguage,com-plicatingtooldevelopmentanddesignereducation.TheseInthispaperweintroduceChisel,anewhardwareconstruc-languagesalsolackthepowerfulabstractionfacilitiesthattionlanguagethatsupportsadvancedhardwaredesignusingar

10、ecommoninmodernsoftwarelanguages,whichleadstohighlyparameterizedgeneratorsandlayereddomain-speciclowdesignerproductivitybymakingitdiculttoreusecom-hardwarelanguages.ByembeddingChiselintheScalapro-ponents.Constructingecienthardwaredesignsrequiresgramminglang

11、uage,weraisethelevelofhardwaredesignab-extensivedesign-spaceexplorationofalternativesystemmi-stractionbyprovidingconceptsincludingobjectorientation,croarchitectures[9]butthesetraditionalHDLshavelimitedfunctionalprogramming,parameterizedtypes,andtypein-modulege

12、nerationfacilitiesandareill-suitedtoproducingference.Chiselcangenerateahigh-speedC++-basedcycle-andcomposingthehighlyparameterizedmodulegeneratorsaccuratesoftwaresimulator,orlow-levelVerilogdesignedtorequiredtosupportthoroughdesign-spaceexploration.Re-maptoeit

13、herFPGAsortoastandardASIC owforsyn-centextensionssuchasSystemVerilogimprovethetypesys-thesis.ThispaperpresentsChisel,itsembeddinginScala,temandparameterizedgeneratefacilitiesbutstilllackmanyhardwareexamples,andresultsforC++simulation,Verilogpowerfulprogramming

14、languagefeatures.emulationandASICsynthesis.Toworkaroundtheselimitations,onecommonapproachistouseanotherlanguageasamacroprocessinglanguageCategoriesandSubjectDescriptorsforanunderlyingHDL.Forexample,Genesis2usesPerltoB.6.3[LogicDesign]:[DesignAids{automaticsynt

15、hesis,providemore exibleparameterizationandelaborationofhardwaredescriptionlanguages]hardwareblockswritteninSystemVerilog[9].ThelanguagecalledVerischemelog[6]providesaSchemesyntaxf