PCIISA接口定义

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1、字串9PinNameDescription引脚名称含义字串8A1/I/OCHCKI/Ochannelcheck;activelow=parityerrorA2D7Databit7A3D6Databit6A4D5Databit5A5D4Databit4A6D3Databit3A7D2Databit2A8D1Databit1A9D0Databit0A10I/OCHRDYI/OChannelready,pulledlowtolengthenmemorycyclesA11AENAddressenable;activehighwhenDMAcontrolsbusA12A

2、19Addressbit19A13A18Addressbit18A14A17Addressbit17A15A16Addressbit16A16A15Addressbit15A17A14Addressbit14A18A13Addressbit13A19A12Addressbit12A20A11Addressbit11A21A10Addressbit10A22A9Addressbit9A23A8Addressbit8A24A7Addressbit7A25A6Addressbit6A26A5Addressbit5A27A4Addressbit4A28A3Addres

3、sbit3A29A2Addressbit2A30A1Addressbit1字串5A31A0Addressbit0B1GNDGroundB2RESETActivehightoresetorinitializesystemlogicB3+5V+5VDCB4IRQ2InterruptRequest2B5-5VDC-5VDCB6DRQ2DMARequest2B7-12VDC-12VDCB8/NOWSNoWaitStateB9+12VDC+12VDCB10GNDGroundB11/SMEMWSystemMemoryWriteB12/SMEMRSystemMemoryRe

4、adB13/IOWI/OWriteB14/IORI/OReadB15/DACK3DMAAcknowledge3B16DRQ3DMARequest3B17/DACK1DMAAcknowledge1B18DRQ1DMARequest1B19/REFRESHRefreshB20CLOCKSystemClock(67ns,8-8.33MHz,50%dutycycle)B21IRQ7InterruptRequest7B22IRQ6InterruptRequest6B23IRQ5InterruptRequest5B24IRQ4InterruptRequest4B25IRQ

5、3InterruptRequest3B26/DACK2DMAAcknowledge2B27T/CTerminalcount;pulseshighwhenDMAterm.countreachedB28ALEAddressLatchEnableB29+5V+5VDCB30OSCHigh-speedClock(70ns,14.31818MHz,50%dutycycle)字串9B31GNDGroundC1SBHESystembushighenable(dataavailableonSD8-15)C2LA23Addressbit23C3LA22Addressbit22C

6、4LA21Addressbit21C5LA20Addressbit20C6LA18Addressbit19C7LA17Addressbit18C8LA16Addressbit17C9/MEMRMemoryRead(Activeonallmemoryreadcycles)C10/MEMWMemoryWrite(Activeonallmemorywritecycles)C11SD08Databit8C12SD09Databit9C13SD10Databit10C14SD11Databit11C15SD12Databit12C16SD13Databit13C17SD

7、14Databit14C18SD15Databit15D1/MEMCS16Memory16-bitchipselect(1wait,16-bitmemorycycle)D2/IOCS16I/O16-bitchipselect(1wait,16-bitI/Ocycle)D3IRQ10InterruptRequest10D4IRQ11InterruptRequest11D5IRQ12InterruptRequest12D6IRQ15InterruptRequest15D7IRQ14InterruptRequest14D8/DACK0DMAAcknowledge0D

8、9DRQ0DMARequest0D10