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1、ARM®andThumb®-2InstructionSetQuickReferenceCardKeytoTablesRm{,}SeeTableRegister,optionallyshiftedbyconstantSeeTableFlexibleOperand2.ShiftandrotateareonlyavailableaspartofOperand2.Acomma-separatedlistofregisters,enclosedinbraces{and}.<
2、fields>SeeTablePSRfields.As,mustnotincludethePC.EitherCPSR(CurrentProcessorStatusRegister)orSPSR(SavedProcessorStatusRegister)As,includingthePC.C*,V*FlagisunpredictableinArchitecturev4andearlier,unchangedinArchit
3、ecturev5andlater.+/-+or–.(+maybeomitted.)4、sh>CanbeRsoranimmediateshiftvalue.Thevaluesallowedforeachshifttypearethesameasthose§SeeTableARMarchitectureversions.showninTableRegister,optionallyshiftedbyconstant.Interruptflags.Oneormoreofa,i,f(abort,int
5、errupt,fastinterrupt).x,yBmeaninghalf-register[15:0],orTmeaning[31:16].SeeTableProcessorModesARM:a32-bitconstant,formedbyright-rotatingan8-bitvaluebyanevennumberofbits.SPmSPfortheprocessormodespecifiedbyThumb:a32-bitconstant,formedbylef
6、t-shiftingan8-bitvaluebyanynumberofbits,orabitLeastsignificantbitofbitfield.patternofoneoftheforms0xXYXYXYXY,0x00XY00XYor0xXY00XY00.Widthofbitfield.+mustbe<=32.SeeTablePrefixesforParallelinstructions{X}RsXisRsrotated16bitsifXpr
7、esent.Otherwise,RsXisRs.{IA
8、IB
9、DA
10、DB}IncrementAfter,IncrementBefore,DecrementAfter,orDecrementBefore.{!}Updatesbaseregisterafterdatatransferif!present(pre-indexed).IBandDAarenotavailableinThumbstate.Ifomitted,defaultstoIA.{S}UpdatesconditionflagsifSpresent.11、ize>B,SB,H,orSH,meaningByte,SignedByte,Halfword,andSignedHalfwordrespectively.{T}UsermodeprivilegeifTpresent.SBandSHarenotavailableinSTRinstructions.{R}RoundsresulttonearestifRpresent,otherwisetruncatesresult.Operation§AssemblerSupdatesActionNotesAddAddADD{S}
12、Rd,Rn,NZCVRd:=Rn+Operand2NwithcarryADC{S}Rd,Rn,NZCVRd:=Rn+Operand2+CarryNwideT2ADDRd,Rn,#Rd:=Rn+imm12,imm12range0-4095T,Psaturating{doubled}5EQ{D}ADDRd,Rm,RnRd:
