发一个PS2接口的VHDL代码

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1、发一个PS2接口的VHDL代码 贴子发表于：2008/11/1617:05:47--HiEmacs,thisis-*-mode:vhdl-*-------------------------------------------------------------------------------------UnidirectionalPS2InteRFace(device->host)--Forconnectmouse/keyboard----ThePS/2mouseandkeyboardimplementabidirectionals

2、ynchronousserial--protocol. Thebusis"idle"whenbothlinesarehigh(open-collector). --THISA*UNIDIRECTIONAL*INTERFACE(DEVICE->HOST)----JavierValcarceGarc韆,javier.valcarce@gmail.com--$Id$----------------------------------------------------------------------------------libraryie

3、ee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;usework.utils.all;entityinterface_ps2is port(   reset  :in std_logic;   clk    :in std_logic;           --fasterthankbclk   kbdata :in std_logic;   kbclk  :in std_logic;   newdata:out

4、std_logic;           --oneclockcyclepulse,notifyanewbytehasarrived   do     :outstd_logic_vector(7downto0)   );endinterface_ps2;-------------------------------------------------------------------------------architecturebehavioralofinterface_ps2is signalst:std_logic; signa

5、lsh:std_logic; signals1      :std_logic; signals2      :std_logic; signalkbclk_fe:std_logic; signalshift9:std_logic_vector(8downto0); signalerror :std_logic; begin---------------------------------------------------------------------------------Edgedetector----------------

6、---------------------------------------------------------------  process(reset,clk) begin   ifreset='1'then     s1<='0';     s2<='0';        elsifrising_edge(clk)then     s2<=s1;     s1<=kbclk;   endif; endprocess; kbclk_fe<='1'whens1='0'ands2='1'else'0';-----------------

7、----------------------------------------------------------------9-bitshiftregistertostorereceiveddata--11-bitframe,LSBfirst:1startbit,8databits,1paritybit,1stopbit------------------------------------------------------------------------------- process(reset,clk) begin   if

8、reset='1'then     shift9<="000000000";   elsifrising_edge(clk)then     ifsh='1'then   shift9(7do