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1、《通信系统FPGA开发》课程设计任务书(适用于通信工程专业)1.设计一数字钟系统,要求如下:(1)有基础的实时数字钟功能,即时,分,秒的正常显示模式。(24小时制)(2)可对系统用手动方式校准,设计两个按键,按动校时键,时计数器加一,按动校分键,则电路处于校分状态。(3)整点报时,要求在59分50秒,52秒,54秒,56秒和58秒发出一个低音信号,00分00秒发出一个高音信号。完整代码加测试代码:modulekongzhi_count(clk,S1,S2,reset,hour_s,hour_g,minute_s,minute_g,second_s,second_g,cout_1,
2、cout_2,alarm_clock_low,alarm_clock_high);inputclk,S1,S2,reset;outputreg[3:0]hour_s,hour_g,minute_s,minute_g,second_s,second_g;outputwirecout_1,cout_2;outputregalarm_clock_low,alarm_clock_high;regR1,R2;always@(posedgeclk)beginif(S1==1)beginR1=1;endelseif(S2==1)beginR2=1;endendalways@(posedgecl
3、k)//秒个位显示beginif(~reset)second_g<=0;elseif(second_g==9)second_g<=0;elsesecond_g<=second_g+1;endalways@(posedgeclk)//秒十位显示beginif(~reset)second_s<=0;elseif(second_g==9)beginif(second_s==5)second_s<=0;elsesecond_s<=second_s+1;endendassigncout_1=((second_g==9)&&(second_s==5))?1:0;always@(posedge
4、clk)//分个位显示beginif(~reset)beginminute_g<=0;endelseif(R2==1)beginif(minute_g==9)minute_g<=0;elsebeginminute_g<=minute_g+1;endR2<=0;endelseif(cout_1)beginsecond_g<=0;second_s<=0;if(minute_g==9)minute_g<=0;elseminute_g<=minute_g+1;endendalways@(posedgeclk)//分十位显示beginif(~reset)beginminute_s<=0;e
5、ndelseif(R2==1)beginif(minute_g==9)beginif(minute_s==5)minute_g<=0;elseminute_s<=minute_s+1;endR2<=0;endelseif(cout_1)beginsecond_g<=0;second_s<=0;if(minute_g==9)beginif(minute_s==5)minute_g<=0;elseminute_s<=minute_s+1;endendendassigncout_2=(((minute_g==9)&&(minute_s==5)&&(cout_1==1))
6、
7、((minu
8、te_g==9)&&(minute_s==5)&&(S2==1)))?1:0;always@(posedgeclk)//时个位显示beginif(~reset)beginhour_g<=0;endelseif(R1==1)beginif(hour_g==9)hour_g<=0;elseif((hour_s==2)&&(hour_g==3))hour_g<=0;elsebeginhour_g<=hour_g+1;endR1<=0;endelseif(cout_2)beginsecond_g<=0;second_s<=0;minute_g<=0;minute_s<=0;if(hour
9、_g==9)hour_g<=0;elseif((hour_s==2)&&(hour_g==3))hour_g<=0;elsehour_g<=hour_g+1;endendalways@(posedgeclk)//时十位显示beginif(~reset)beginhour_s<=0;endelseif(R1==1)beginif((hour_g==3)&&(hour_s==2))hour_s<=0;elseif(hour_g==9)beginhour_s<=hour_s+1;end