资源描述：
《基于vhdl的计时系统方案的设计研究》由会员上传分享，免费在线阅读，更多相关内容在工程资料-天天文库。
1、摘要本次设计是通过使用VHDL语言设计了一个综合的计时系统，能实现年、月、日、时、分、秒、星期的计数综合计时功能，同时将计时结果用15个七段数码管显示，并且可通过两个设置键对计时系统有关的参数进行调整。综合计时电路可分为计年电路、计月电路、计日电路、计时电路、计分电路、计秒电路、计星期电路等7个子模块，这7个子模块都具有预置、计数和进位功能。关键词:VHDL；计时系统AbstractUsingtheVHDLlanguagedesigntimingsystem,acomprehensivesystemtoachieve
2、theyear,month,day,hour,minuteandsecondweeksofcountingandtimingfunctionssuchasintegrated,whiletimingtheresultsof15seven-segmentdigitaldisplay,andcanbesetbytwokeysystemparametersonthetimingadjustment.Timingcircuitintegratedcircuitcanbedividedintotheseconds,scorin
3、gcircuit,timingcircuit,namely,onthecircuit,monthlycircuit,namely,7-weekcircuitsub-module,whichhasapreset7sub-module,counting,andcarryfunction.Keywords:VHDL；Timingsystem目录摘要································································I31Abstract··············
4、··············································II1前言·····························································11.1计时系统研究背景·············································11.2设计要求·····················································11.3设计方案与方案优点··················
5、·························21.4设计的可行性·················································32外围电路设计······················································42.1电源设计······················································42.2方波信号源设计··········································
6、·····52.2.1晶振电路31··················································52.2.2分频电路··················································62.3七段数码显示电路·············································72.4总体电路设计·················································93VHDL内部电路设计······
7、·········································103．1综合计时电路设计············································103.1.1计秒电路设计············································103.1.2计分电路设计············································123.1.3计时电路设计····································
8、········123.1.4计日电路设计············································13313.1.5计月电路················································153.1.6计年电路设计··································
