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ID:15710964
大小:924.00 KB
页数:57页
时间:2018-08-05
《多周期mpis指令集设计》由会员上传分享,免费在线阅读,更多相关内容在教育资源-天天文库。
1、指令类型[31:26][25:21][20:16][15:11][10:6][5:0]R类型OpRsRtRdshamtfunct含义nop00000000000000000000000000000000空操作addu000000rsrtrd00000100001加(不带溢出)subu000000rsrtrd00000100011减(不带溢出)and000000rsrtrd00000100100与or000000rsrtrd00000100101或xor000000rsrtrd00000100110异或nor000000rsrtrd00000100111或非sllv000000r
2、srtrd00000000100逻辑左移变量srlv000000rsrtrd00000000110逻辑右移变量I类型OpRsRtimmediatebltz000001rs00000Immediate小于0转移beq000100rsrtImmediate相等转移bne000101rsrtImmediate不相等转移addi001000rsrtImmediate加立即数andi001100rsrtImmediate与立即数ori001101rsrtImmediate或立即数lw100011rsrtImmediate取字sw101011rtrtImmediate存字J类型OpAddr
3、essj000010address无条件跳转综述:本设计选用了如下指令,基于此设计出了单周期MIPS处理器,并在单周期的基础上添加了5级流水线设计出了带五级流水线的MIPS处理器。第一部分单周期MIPS处理器一、代码------------------------------------------------------------------------------------ModuleName:top_mips-Behavioral顶层模块------------------------------------------------------------------
4、----------------libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entitytop_mipsisport(reset:instd_logic;clk:instd_logic;ov:outstd_logic);endtop_mips;architectureBehavioraloftop_mipsissignals_pc:std_logic_vector(31downto0);---pc输入signals_pc_i:s
5、td_logic_vector(31downto0);---pc输出signals_command:std_logic_vector(31downto0);---指令signals_add1_pc:std_logic_vector(31downto0);---pc+1值signals_shift:std_logic_vector(27downto0);--指令低26位左移2位后值signals_jump_pc:std_logic_vector(31downto0);--绝对跳转signals_regdst:std_logic;----控制信号signals_jump:std_l
6、ogic;signals_branch:std_logic;signals_memread:std_logic;signals_memtoreg:std_logic;signals_aluop:std_logic_vector(3downto0);signals_memwrite:std_logic;signals_alusrc:std_logic;signals_regwrite:std_logic;signals_opa:std_logic_vector(31downto0);----ALU操作数signals_opb:std_logic_vector(31downto0)
7、;----ALU操作数signals_reg_data:std_logic_vector(31downto0);--寄存器读出的第二个数据signals_imm_data:std_logic_vector(31downto0);---低16位符号扩展后signals_zero:std_logic;signals_alu_result:std_logic_vector(31downto0);signals_branch_pc:std_logic_vector(31downto0);----条件
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