最新主板信号量测教学讲义PPT课件.ppt

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1、主板信号量测HoldCommonClockDataTransferD0D1D2D0D1D2ClockDriverDrivingReceivingTcoFlightTimeSetup1234DefiningTcoDinClockOutputBufferInternalLogicRL=50WClockrisest=0VmeasTcoLoadforTcomeasurement(fromdatabook)Tco=timefromclockrisetoVmeasintotestloadClockJitterC

2、lockDriverCycle1Cycle2ClockJitteroccurswhentheclockperiodvariesfromoneperiodtothenextUsuallycausedbyPLLinstabilityintheclockdriverJitterincreases/decreasestheclockperiod,decreasingtheeffectiveclockcycleClockSkewD0D1D2ClockDriverD0D1D2t=0t=1t=2Occurswhend

3、ifferentdevicesseetheclocktransitionatdifferenttimesIncreases/decreasestheapparentclockcycle.Dependingonwhichdevicesaredriving/receivingReducestheeffectiveclockcycleBusClockCycleBudgetingForeachDriverReceiverpath:Tflightmax

4、ew-Jitter-Crosstalk-Receiver(Setup)Tflightmin>Receiver(Hold)-Driver(Tcomin)+Skew+CrosstalkDriver(Tcomax)Tflightmax+/-Jitter+/-SkewReceiver(Setup)Receiver(Hold)+/-Crosstalk+/-CrosstalkCommonClockBusExampleIntelP

5、entium-ProreferencedesignProcessor/ChipsetBus(GTL+,66MHz)IntelGTL+DesignGuidelinesDefiningDeviceTimingTimingstakenfrom“AC(dynamic)Specifications”sectionsofInteldatasheetsMostdatasheetsavailableviaWWWImportantparametersClockDataValidforGTL+BusSetup/Hol

6、drequirementsforGTL+signalsPLLJitter(ifspec’d)PentiumPro440FX(timingsfrom440LX)DeterminingFlightTimesTflightmax=4.50nsTflightmin=0.45nsSignalWavePropagationFlighttimet1=L/cc6.5in/nsTflightmax=4.50nsTflightmin=0.45ns29in>L>3inRiskOhm’slaw?i=(va-vb)/Rtra

7、cei→∞whenRtrace→0ModeloftransmissionlineSignalWavePropagationFlighttimet1=L/cv1=VoltagePartitionforR0&z0R0z0v1v2v2=VoltagePartitionforR0&RLRLImpedanceChangeLayerchangeReferenceplanecrossingTracesplittingSeriescomponentConnectorPullhigh&pulldownImpedanceC

8、hangeLayerchangeReferenceplanecrossingTracesplittingSeriescomponentConnectorPullhighSchematicsvs.LayoutVccMicrostripSectionhtwerZo=f(w,h,t,er)Zo=Characteristicimpedance(W)w=Widthoftrace(mils)t=Thicknessoftrace(mils)h=Thick