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1、LIBRARYIEEE;USEIEEE.std_logic_1164.ALL;ENTITYhalf_adderIS--一位半加器PORT(A,B:INstd_logic;Co:OUTstd_logic;S:OUTstd_logic);ENDhalf_adder;ARCHITECTURErtlOFhalf_adderISSIGNALtmp1,tmp2:std_logic;BEGINtmp1<=AORB;tmp2<=ANANDB;Co<=NOTtmp2;S<=tmp1ANDtmp2;ENDrtl;LI
2、BRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYOR_2IS--或门PORT(A,B:INSTD_LOGIC;C:OUTSTD_LOGIC);ENDENTITYOR_2;ARCHITECTUREARTOFOR_2ISBEGINC<=AORB;ENDARCHITECTUREART;LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYfull_adderIS--结构描述法设计一位全加器PORT(A,B,Cin:INSTD_LO
3、GIC;S,Co:OUTSTD_LOGIC);ENDfull_adder;ARCHITECTUREstructureOFfull_adderISSIGNALtmp1,tmp2,tmp3:std_logic;COMPONENThalf_adderPORT(A,B:INstd_logic;Co:OUTstd_logic;S:OUTstd_logic);ENDCOMPONENT;COMPONENTOR_2PORT(a,b:INstd_logic;c:OUTstd_logic);ENDCOMPONENT;
4、BEGINU0:half_adderPORTMAP(A,B,tmp2,tmp1);U1:half_adderPORTMAP(tmp1,Cin,tmp3,S);U2:OR_2PORTMAP(tmp3,tmp2,Co);ENDstructure;LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYfull_adder_4ISPORT(X,Y:INSTD_LOGIC_VECTOR(1TO4);C:INSTD_LOGIC;SUM:OUTSTD_LOGIC_VECTOR
5、(1TO4);CO:OUTSTD_LOGIC);ENDfull_adder_4;ARCHITECTUREstructOFfull_adder_4IS--结构描述法设计四位全加器COMPONENTfull_adderPORT(A,B,Cin:INSTD_LOGIC;S,CO:OUTSTD_LOGIC);ENDCOMPONENT;SIGNALtemp1,temp2,temp3,temp4:STD_LOGIC;BEGINU1:full_adderPORTMAP(X(1),Y(1),C,SUM(1),te
6、mp1);U2:full_adderPORTMAP(A=>X(2),B=>Y(2),Cin=>temp1,S=>SUM(2),Co=>temp2);U3:full_adderPORTMAP(A=>X(3),B=>Y(3),Cin=>temp2,S=>SUM(3),Co=>temp3);U4:full_adderPORTMAP(A=>X(4),B=>Y(4),Cin=>temp3,S=>SUM(4),Co=>temp4);CO<=temp4;ENDstruct;
