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1、1.1程序的结构library、entity、port1.2设计的表达architecture、signal1.3结构表达与运算表达1.4数字系统的进程表达process第一章VHDL对电路设计的基本描述VHDL与数字集成电路设计VHDL的构造体：architecture1.2设计的表达architecture、signal实体与构造体的关系1.2设计的表达architecture、signalUSEWORK.std_logic_1164.ALL;ENTITYdecodeISPORT(a,b,en:INstd_logic;q0,q1,q2,q3:OUTstd_logic);E
2、NDdecode;实体与构造体的关系1.2设计的表达architecture、signalARCHITECTUREstructuralOFdecodeISCOMPONENTinvPORT(a:INstd_logic;b:OUTstd_logic);ENDCOMPONENT;COMPONENTand3PORT(a1,a2,a3:INstd_logic;o1:OUTstd_logic);ENDCOMPONENT;SIGNALnota,notb:std_logic;BEGINI1:invPORTMAP(a,nota);I2:invPORTMAP(b,notb);A1:and3POR
3、TMAP(nota,en,notb,Q0);A2:and3PORTMAP(a,en,notb,Q1);A3:and3PORTMAP(nota,en,b,Q2);A4:and3PORTMAP(a,en,b,Q3);ENDstructural;1.2设计的表达architecture、signal低级配置：对解码器实体低级形式的元件配置如下：CONFIGURATIONdecode_llconOFdecodeISFORstructuralFORI1:invUSECONFIGURATIONWORK.invcon(behav);ENDFOR;FORI2:invUSECONFIGURAT
4、IONWORK.invcon(behav);;ENDFOR;FORALL:and3USECONFIGURATIONWORK.and3con(behav);ENDFOR;ENDstructural;ENDdecode_llcon;实体与构造体的关系1.2设计的表达architecture、signalUSEWORK.std_logic_1164.ALL;ENTITYinvISPORT(a:INstd_logic;b:OUTstd_logic);ENDinv;ARCHITECTUREbehaveOFinvISBEGINb<=NOT(a)AFTER5ns;ENDbehave;CON
5、FIGURATIONinvconOFinvISFORbehaveENDFOR;ENDinvcon;实体与构造体的关系1.2设计的表达architecture、signalUSEWORK.std_logic_1164.ALL;ENTITYand3ISPORT(a1,a2,a3:INstd_logic;o1:OUTstd_logic);ENDand3;ARCHITECTUREbehaveOFand3ISBEGINo1<=a1ANDa2ANDa3AFTER5ns;ENDbehave;CONFIGURATIONand3conOFand3ISFORbehaveENDFOR;ENDand
6、3con;1.2设计的表达architecture、signalUSEWORK.std_logic_1164.ALL;ENTITYcounterISPORT(load,clear,clk:INstd_logic;data_in:ININTEGER;data_out:OUTINTEGER);ENDcounter;ARCHITECTUREcount_255OFcounterISBEGINPROCESS(clk)……..…….ENDPROCESS;ENDcount_255;ARCHITECTUREcount_64kOFcounterISBEGINPROCESS(clk)……..……
7、….ENDPROCESS;ENDcount_64k;CONFIGURATIONsmall_countOFcounterISFORcount_255ENDFOR;ENDsmall_count;CONFIGURATIONbig_countOFcounterISFORcount_64kENDFOR;ENDbig_count;构造体表达一个实体的内部细节：运算功能、器件连接。VHDL的构造体：architecture1.2设计的表达architecture、signalarchitecturearch_name
