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1、DESIGNOFCMOSCMLCIRCUITSFORHIGH-SPEEDBROADBANDCOMMUNICATIONSMichaelM.Green&UllasSinghDept.ofElectrical&ComputerEngineeringUniv.ofCalifornia,IrvineABSTRACT2.HIGH-SPEEDBROADBANDSIGNALSANDCIRCUITBEHAVIORThispaperdiscussesthebehavioranddesignofCMOScurrent-Abroadbandcommunic
2、ationscircuitprocesseshigh-speedmodelogic’.(CML)circuits.Theadvantagesofusingthedigitalsignals.InsuchcircuitsaccuracyisrequirednotCMLtopologyoverstaticCMOSforhigh-speeddigitalsig-inthevoltagedomain,hutinthetimedomain-thatis,nalsarediscussed.BiasinganddynamicbehaviorofC
3、MLthetimingoflogicleveltransitionsmustheveryprecise.circuitsarediscussedandadesignmethodforoptimizingThenonlinearbehaviorofaproperlydesignedlogicgatethebandwidthandspeedispresented.willcorrectanydeviationsintheinputsignallevel(i.e..aslongasthevoltagesarewithinthespecif
4、iednoisemargins,theirexactvaluesareunimportant),hutwillnotcorrectanytimedeviationthatmayoccurinaninputdatatransition.1.INTRODUCTIONSuchdeviationsareingeneralcalled“jitter.”Randomjitterisnormallycausedbynoisegeneratedbyorcoupledintotheblocksthatgeneratethesynchronizatio
5、nsignalsfortheAll-CMOStransceiversforSONETapplicationsoperatingcircuit(e.g.,phase-lockedloop)whiledeterministicjitterat2.5Gh/s[I]and,morerecently,at10Gh/s[2,3,41haveiscausedbynon-idealitiesinthedatapathcircuitsthem-recentlybeenreported.Thehighspeedsrequiredfortheseselv
6、es.Inthispaperweareprimarilyinterestedindeter-circuitsareachievedbyuseofcurrent-modelogic(CML)ministicjitter.Therearetwomaincausesofdeterministiccircuittopologies.ACMOSCMLbuffer,showninFig.2,jitter.Intersymbolinterference(ISI)occurswhentheris-consistsofaconventionaldif
7、ferentialpairwithdimensionsinglfallingtimeconstant7ofacircuitisnotmuchsmallerl47/L,aresistiveloadR,andatailcurrentsourceIss.thanaunitinterval(UI),asillustratedinFig.1.Ingeneral,TheseparametersmusthechosencarefullytooptimizetheIS1ishighlydatadependent;theamountofjitterc
8、ausedbycircuit’sperformancewithregardtospeed,area,powerdis-IS1willdependonhowoftenisolatedsingle-U1pulseswillsipation
