Clock domain cross design and verification.pdf

Clock domain cross design and verification.pdf

ID:33939952

大小:1.72 MB

页数:56页

时间:2019-03-01

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1、SNUG-2008Boston,MAVotedBestPaper1stPlaceWorldClassVerilog&SystemVerilogTrainingClockDomainCrossing(CDC)Design&VerificationTechniquesUsingSystemVerilogCliffordE.CummingsSunburstDesign,Inc.cliffc@sunburst-design.comABSTRACTImportantdesignconsiderationsrequirethatmulti-clockdesignsbecarefullyconstr

2、uctedatClockDomainCrossing(CDC)boundaries.ThispaperdetailssomeofthelateststrategiesandbestknownmethodstoaddresspassingofoneandmultiplesignalsacrossaCDCboundary.IncludedinthepaperaretechniquesrelatedtoCDCverificationandaninteresting2-deepFIFOdesignforpassingmultiplecontrolsignalsbetweenclockdomai

3、ns.AlthoughthedesignmethodsdescribedinthepapercanbegenerallyimplementedusinganyHDL,theexamplesareshownusingefficientSystemVerilogtechniques.TableofContents1.0Introduction...........................................................................................................................62.

4、0Metastability..........................................................................................................................62.1Whyismetastabilityaproblem?...........................................................................................73.0Synchronizers.....................

5、...................................................................................................83.1Twosynchronizationscenarios.............................................................................................83.2Twoflip-flopsynchronizer.............................................

6、......................................................83.3MTBF-meantimebeforefailure.........................................................................................93.4Threeflip-flopsynchronizer.............................................................................................

7、..103.5Synchronizingsignalsfromthesendingclockdomain.......................................................103.6Synchronizingsignalsintothereceivingclockdomain......................................................114.0Synchr

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