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1、ClockVerificationinthePresenceofIR-DropinthePowerDistributionNetworkSyedZakirHussain,SteftenRochel,DavidOverhauser,ResveSalehSirnplexSolutionsInc.Abstracterablevoltagedropinthepowergrid.Thisvoltagedrop,alsoknownasIR-drop,variesdynamically,asitisrelatedClocknetsare
2、themostimportantcircuitsinhigh-speedtotheswitchingactivityoftheclocksignal.Thefluctua-digitalsystems.Thedesignofclockcircuitryandthetionofthesupplyvoltagecausesvariationsinthedelay,qualityoftheclocksignaldirectlyimpactstheperfor-skew,andslewratesandresultsinclocks
3、ignaljitter.TheremanceofaVLSIchip.Clockverificationrequireshighareseveraldesignmethodologiesavailable,suchaspower-accuracyandistypicallyperformedusingcircuitsimula-supplyvoltagescaling,gated-clocks[2],andnon-zerotors.Inhigh-performancedeep-submicrondigitalcircuits
4、,skew,toreduceinstantaneouspowerdissipation.clocksarerunningathigherfrequenciesandaredrivingmoregatesthanever,thuspresentingahigherloadontheInthepresenceoflargeparasiticdevicesandprocessvari-powerdistributionnetworkwiththepotentialofsutbstan-ations,theverification
5、ofclocknetworksbeforefabrica-tialIR-drop.However,asIR-dropisafull-chipphenome-tionisimperative.Indifferentphasesofclockdesign,non,circuitsimulationisextremelytimeconsuming.Inperformancecanbeverifiedusingstaticaswellasthispaper,wepresentalooselycouplediterativetecl
6、hniquedynamicanalysis.Intheearlystages,statictiminganaly-forclockverificationinthepresenceoffull-chipdynamicsiscanprovidearoughestimateofthesignaldelays.How-IR-drop.Thedegradationintheclocksignalduetoever,forrealisticclockanalysis,accurate3DparasiticdynamicIR-drop
7、isdemonstratedonasmallexampleasextractionanddynamicanalysiswithaccuracycompara-wellasuponalargechip.Inaddition,wealsodiscusisrisksbletocircuitsimulationisrequired.associatedwithassumingastaticIR-dropbudgetuponclockpropagation.Power-gridIR-dropisafull-chipphenomeno
8、n.Thecur-rentdrawnbyanydeviceconnectedtoapowergridcon-1.Introductiontributestoavoltagedropatallnodesofthegrid.AtIntherecentyears,therehasbeenconsiderabl
