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1、序向邏輯與正反器設計第八章儒林圖書公司SIM896aVHDL數位電路設計實務教本第三版1Process敘述和If_then_else標記名稱:Process（SensitivityList）beginProcess主體敘述EndProcess標記名稱;If(條件1)Then指令敘述;Elsif(條件2)Then指令敘述;：Else指令敘述;EndIf;If_Then_Else比較指令Process敘述2if_then_else敘述-D型正反器CLKDQ(t+1)0XQ(t)1XQ(t)↑11↑00LIBRARYIEEE;USEIEEE.STD_LOGIC_1
2、164.ALL;ENTITYdff_visPORT(CLK,D:INSTD_LOGIC;Q:OUTSTD_LOGIC);ENDdff_v;ARCHITECTUREaOFdff_vISBEGINPROCESS(CLK)BEGINIFCLK'eventANDCLK='1'THENQ<=D;ENDIF;ENDPROCESS;ENDa;clkevent3if_then_else敘述-AND閘的模擬ABClibraryIEEE;useIEEE.std_logic_1164.all;entityAND2_vhdlisport(A,B:inSTD_LOGIC;C:outS
3、TD_LOGIC);endAND2_vhdl;architectureaofAND2_vhdlisbeginprocess(A,B)beginif(A='0')and(B='0')thenC<='0';elsif(A='0')and(B='1')thenC<='0';elsif(A='1')and(B='0')thenC<='0';elsif(A='1')and(B='1')thenC<='1';endif;endprocess;enda;--definetheprocesssection--thesensitivitylist4if_then_else敘述
4、-半加法器設計輸入輸出xycarrysum0000010110011110libraryIEEE;useIEEE.std_logic_1164.all;entityhalfadd_vhdlisport(x,y:inSTD_LOGIC;sum,carry:outSTD_LOGIC);endhalfadd_vhdl;architectureaofhalfadd_vhdlisbeginprocess(x,y)beginif(x='0')and(y='0')thencarry<='0';sum<='0';elsif(x='0')and(y='1')thencarry
5、<='0';sum<='1';elsif(x='1')and(y='0')thencarry<='0';sum<='1';elsif(x='1')and(y='1')thencarry<='1';sum<='0';endif;endprocess;enda;5if_then_else敘述-四對一多工器方法一：單層的IF-Then-else敘述LibraryIEEE;Useieee.std_logic_1164.all;EntityMUX41ISPORT(A,B,C,D:INstd_logic;S:INstd_logic_vector(1downto0);X:
6、OUTstd_logic);ENDMUX41;ArchitectureAofMUX41ISBEGINPROCESS(s,a,b,c,d)BEGINif(s="00")thenX<=a;elsif(s="01")thenX<=b;elsif(s="10")thenX<=c;elseX<=d;endif;ENDPROCESS;ENDa;6if_then_else敘述-四對一多工器方法二：三層巢狀的IF-Then-else敘述LibraryIEEE;Useieee.std_logic_1164.all;EntityMUX41bISPORT(A,B,C,D:INst
7、d_logic;S:INstd_logic_vector(1downto0);X:OUTstd_logic);ENDMUX41b;ArchitectureAofMUX41bISBEGINROCESS(s,a,b,c,d)BEGINif(s="00")thenX<=a;elseif(s="01")thenX<=b;elseif(s="10")thenX<=c;elseX<=d;endif;endif;endif;ENDPROCESS;ENDa;7if_then_else敘述-三態緩衝閘libraryIEEE;useIEEE.std_logic_1164.all
8、;entitytri_gateisport(oe,X
